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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit serial daisy-chain cmos d/a converter DAC8143 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features fast, flexible, microprocessor interfacing in serially controlled systems buffered digital output-pin for daisy-chaining multiple dacs minimizes address-decoding in multiple dac systemsth ree wire interface for any number of dacs one data line one clk line one load line improved resistance to esd C40 8 c to +85 8 c for the extended industrial temperature range available in die form applications multiple-channel data acquisition systems process control and industrial automation test equipment remote microprocessor-controlled systems general information the DAC8143 is a 12-bit serial-input daisy-chain cmos d/a converter, which features serial data input and buffered serial data output. it was designed for multiple serial dac systems, where serially daisy-chaining one dac after another is greatly simplified. the DAC8143 also minimizes address decoding lines enabling simpler logic interfacing. it allows 3-wire interface for any num- ber of dacs: one data line, one clk line, and one load line. serial data in the input register (msb first) is sequentially clocked out to the sro pin as the new data word (msb first) is simultaneously clocked in from the sri pin. the strobe inputs are used to clock in/out data on the rising or falling (user selected) strobe edges (stb 1 , stb 2 , stb 3 , stb 4 ). when the shift register's data has been updated, the new data word is transferred to the dac register with use of ld 1 and ld 2 inputs. separate load control inputs allow simultaneous output up- dating of multiple dacs. an asynchronous clear input re- sets the dac register without altering data in the input register. improved linearity and gain error performance permits reduced circuit parts count through the elimination of trimming compo- nents. also, fast interface timing reduces timing design consid- eration while minimizing microprocessor wait states. functional block diagram 12-bit d/a converter input 12-bit shift register in out clk load dac register DAC8143 15 13 5 9 4 10 11 8 7 12 6 3 2 1 16 14 dgnd v ref clr ld 1 ld 2 stb 1 v dd stb 4 stb 3 stb 2 sri r fb i out1 i out2 agnd sro the DAC8143 is available in standard cerdip and plastic pack- ages that are compatible with auto-insertion equipment. cerdip and plastic packages devices come in the extended in- dustrial temperature range of C40 c to +85 c. multiple DAC8143s with 3-wire interface strobe sri sro DAC8143 load address decoder address bus strobe sri sro DAC8143 load strobe sri sro DAC8143 load strobe sri sro DAC8143 load wr db x ?
electrical characteristics parameter symbol conditions min typ max units static accuracy resolution n 12 bits nonlinearity 1 inl DAC8143a/e 1/2 lsb DAC8143f 1 lsb differential nonlinearity 2 dnl DAC8143a/e 1/2 lsb DAC8143f 1 lsb gain error 3 g fse t a = +25 c DAC8143a/e 1 lsb DAC8143f 2 lsb t a = full temperature range (all grades) 2 lsb gain tempco ( d gain/ d temp) 4 tc gfs 5 ppm/ c power supply rejection ratio ( d gain/ d v dd ) psrr d v dd = 5% 0.0006 0.002 %/% output leakage current 5 i lkg t a = +25 c 5na t a = full temperature range DAC8143a 100 na DAC8143e/f 25 na zero scale error 6, 7 i zse t a = +25 c 0.002 0.03 lsb t a = full temperature range DAC8143a 0.05 0.61 lsb DAC8143e/f 0.01 0.15 lsb input resistance 8 r in v ref pin 7 11 15 k w ac performance output current settling time 4, 9 t s 0.380 1 m s ac feedthrough error (v ref to i out1 ) 4, 10 ft v ref = 20 v p-p @ f = 10 khz, t a = +25 c 2.0 mv p-p digital-to-analog glitch energy 4, 11 qv ref = 0 v, i out load = 100 w , c ext = 13 pf 20 nvs total harmonic distortion 4 thd v ref = 6 v rms @ 1 khz dac register loaded with all 1s C92 db output noise voltage density 4, 12 e n 10 hz to 100 khz between r fb and i out 13 nv/ ? hz digital inputs/output digital input high v ih 2.4 v digital input low v il 0.8 v input leakage current 13 i in v in = 0 v to +5 v 1 m a input capacitance c in v in = 0 v 8 pf digital output high v oh i oh = C200 m a4v digital output low v ol i ol = 1.6 ma 0.4 v analog outputs output capacitance 4 c out1 digital inputs = all 1s 90 pf c out2 digital inputs = all 0s 90 pf output capacitance 4 c out1 digital inputs = all 0s 60 pf c out2 digital inputs = all 1s 60 pf timing characteristics 4 serial input to strobe setup times t ds1 stb 1 used as the strobe 50 ns (t stb = 80 ns) t ds2 stb 2 used as the strobe 20 ns t ds3 stb 3 used as the strobe t a = +25 c10 ns t a = full temperature range 20 ns t ds4 stb 4 used as the strobe 20 ns t dh1 stb 1 used as the strobe t a = +25 c40 ns t a = full temperature range 50 ns t dh2 stb 2 used as the strobe t a = +25 c50 ns t a = full temperature range 60 ns serial input to strobe hold times (t stb = 80 ns) t dh3 stb 3 used as the strobe 80 ns t dh4 stb 4 used as the strobe 80 ns rev. b C2C (@ v dd = +5 v; v ref = +10 v; v out1 = v out2 = v agnd = v dgnd = 0 v; t a = full temperature range specified under absolute maximum ratings, unless otherwise noted.) DAC8143Cspecifications
electrical characteristics DAC8143 parameter symbol conditions min typ max units stb to sro propagation delay 14 t a = +25 c 220 ns t pd t a = full temperature range 300 ns sri data pulse width t sri 100 ns stb 1 pulse width (stb 1 = 80 ns) 15 t stb1 80 ns stb 2 pulse width (stb 2 = 100 ns) 15 t stb2 80 ns stb 3 pulse width (stb 3 = 80 ns) 15 t stb3 80 ns stb 4 pulse width (stb 4 = 80 ns) 15 t stb4 80 ns load pulse width t ld1 , t ld2 t a = +25 c 140 ns t a = full temperature range 180 ns lsb strobe into input register to load dac register time t asb 0ns clr pulse width t clr 80 ns power supply supply voltage v dd 4.75 5 5.25 v all digital inputs = v ih or v il 2ma supply current i dd all digital inputs = 0 v or v dd 0.1 ma digital inputs = 0 v or v dd power dissipation p d 5 v 0.1 ma 0.5 mw digital inputs = v ih or v il 5 v 2 ma 10 mw notes 1 1 1/2 lsb = 0.012% of full scale. 1 2 all grades are monotonic to 12-bits over temperature. 1 3 using internal feedback resistor. 1 4 guaranteed by design and not tested. 1 5 applies to i out1 ; all digital inputs = v il , v ref = +10 v; specification also applies for i out2 when all digital inputs = v ih . 1 6 v ref = +10 v, all digital inputs = 0 v. 1 7 calculated from worst case r ref : i zse (in lsbs) = (r ref i lkg 4096) /v ref . 1 8 absolute temperature coefficient is less than +300 ppm/ c. 9 i out , load = 100 w . c ext = 13 pf, digital input = 0 v to v dd or v dd to 0 v. extrapolated to 1/2 lsb: ts = propagation delay (t pd ) +9 t , where t equals measured time constant of the final rc decay. 10 all digital inputs = 0 v. 11 v ref = 0 v, all digital inputs = 0 v to v dd or v dd to 0 v. 12 calculations from e n = ? 4k trb where: k = boltzmann constant, j/ kr = resistance w t = resistor temperature, k b = bandwidth, hz 13 digital inputs are cmos gates; i in typically 1 na at +25 c. 14 measured from active strobe edge (stb) to new data output at sro; c l = 50 pf. 15 minimum low time pulse width for stb 1 , stb 2 , and stb 4 , and minimum high time pulse width for stb 3 . specifications subject to change without notice. @ v dd = +5 v; v ref = +10 v; v out1 = v 0ut2 = v agnd = v dgnd = 0 v; t a = full temperature range specified under absolute maximum ratings, unless otherwise noted. DAC8143 C3C rev. b
DAC8143 C4C rev. b 1. i out1 1 9. ld 2 2. i out2 10. stb 3 3. agnd 11. stb 4 4. stb 1 12. dgnd 5. ld 1 13. clr 6. sr0 14. v dd (substrate) 7. sri 15. v ref 8. stb 2 16. r fb substrate (die backside) is internally connected to v dd . for additional dice information, refer to 1990/91 data- book, section 2. dice characteristics die size 0.099 x 0.107 inch, 10,543 sq. mils (2.51 x 2.72 mm, 6.83 sq. mm) DAC8143g parameter symbol conditions limits units static accuracy resolution n 12 bits min integral nonlinearity inl 1 lsb max differential nonlinearity dnl 1 lsb max gain error g fse using internal feedback resistor 2 lsb max power supply rejection ratio psrr d v dd = ?5% 0.002 %/% max output leakage current (i out1 )i lkg digital inputs = v il 5 na max reference input input resistance r in v ref pad 7/15 k w min/max digital inputs/output digital input high v ih 2.4 v min digital input low v il 0.8 v max input leakage current i il v in = 0 v to v dd 1 m a max digital output high v oh i oh = C200 m a 4 v min digital output low v ol i ol = 1.6 ma 0.4 v max power supply supply current i dd digital inputs = v ih or v il 2.0 ma max digital inputs = 0 v or v dd 0.1 ma max note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. wafer test limits at v dd = +5 v; v ref = +10 v; v out1 = v out2 = v agnd = v dgnd = 0 v, t a = +25 8 c. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the DAC8143 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
DAC8143 C5C rev. b pin connections 16-pin epoxy dip (p suffix), 16-pin cerdip (q suffix) 16-pin sol (s suffix) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 i out1 i out2 agnd stb 1 ld 1 sro sri stb 2 r fb v ref v dd clr dgnd stb 4 stb 3 ld 2 absolute maximum ratings (t a = +25 c, unless otherwise noted.) v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 v v ref to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v v rfb to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . v dd + 0.3 v dgnd to agnd . . . . . . . . . . . . . . . . . . . . . . . . v dd + 0.3 v digital input voltage range . . . . . . . . . . . . . . . C0.3 v to v dd output voltage (pin 1, pin 2) . . . . . . . . . . . . . . C0.3 v to v dd operating temperature range aq version . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c eq/fp/fs versions . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . +300 c package type u ja 1 u jc units 16-pin hermetic dip (q) 94 12 c/w 16-pin plastic dip (p) 76 33 c/w 16-pin sol (s) 92 27 c/w note 1 q ja is specified for worst case mounting conditions, i.e., q ja is specified for device in socket for cerdip and p-dip packages; q ja is specified for device soldered to printed circuit board for sol package. caution 1. do not apply voltage higher than v dd or less than dgnd po- tential on any terminal except v ref (pin 15) and r fb (pin 16). 2. the digital control inputs are zener-protected; however, per- manent damage may occur on unprotected units from high energy electrostatic fields. keep units in conductive foam at all times until ready to use. 3. use proper antistatic handling procedures. 4. absolute maximum ratings apply to both packaged devices and dice. stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the device. ordering information 1 gain temperature package model nonlinearity error range description DAC8143aq 1/2 lsb 1 lsb C55 c to +125 c 16-lead cerdip DAC8143aq/883 2 1/2 lsb 1 lsb C55 c to +125 c 16-lead cerdip DAC8143eq 1/2 lsb 1 lsb C40 c to +85 c 16-lead cerdip DAC8143fp 1 lsb 2 lsb C40 c to +85 c 16-lead plastic dip DAC8143fs 3 1 lsb 2 lsb C40 c to +85 c 16-lead sol notes 1 burn-in is available on commercial and industrial temperature range parts in cerdip and plastic dip. 2 for devices processed in total compliance to mil-std-883, add /883 after part number. consult factory for 883 data sheet. 3 for availability and burn-in information on so and plcc packages, contact your local sales office.
DAC8143 C6C rev. b multiplying mode frequency response vs. digital code multiplying mode total harmonic distortion vs. frequency supply current vs. logic input voltage linearity error vs. digital code linearity error vs. reference voltage logic threshold voltage vs. supply voltage dnl error vs. reference voltage digital output voltage vs. output current Ctypical performance characteristics
DAC8143 C7C rev. b either i out1 or i out2 . switching current to i out1 or i out2 yields a constant current in each ladder leg, regardless of digital input code. this constant current results in a constant input resis- tance at v ref equal to r (typically 11 k w ). the v ref input may be driven by any reference voltage or current, ac or dc, that is within the limits stated in the absolute maximum ratings chart. the twelve output current-steering switches are in series with the r-2r resistor ladder, and therefore, can introduce bit errors. it was essential to design these switches such that the switch on resistance be binarily scaled so that the voltage drop across each switch remains constant. if, for example, switch 1 of figure 1 was designed with an on resistance of 10 w , switch 2 for 20 w , etc., a constant 5 mv drop would then be main- tained across each switch. to further insure accuracy across the full temperature range, permanently on mos switches were included in series with the feedback resistor and the r-2r ladders terminating resistor. the simplified dac circuit, figure 1, shows the location of these switches. these series switches are equivalently scaled to two times switch 1 (msb) and top switch 12 (lsb) to maintain constant relative voltage drops with varying temperature. dur- ing any testing of the resistor ladder or r feedback (such as in- coming inspection), v dd must be present to turn on these series switches. figure 1. simplified dac circuit specification definitions resolution the resolution of a dac is the number of states (2 n ) that the full-scale range (fsr) is divided (or resolved) into, where n is equal to the number of bits. settling time time required for the analog output of the dac to settle to within 1/2 lsb of its final value for a given digital input stimu- lus; i.e., zero to full-scale. gain ratio of the dacs external operational amplifier output voltage to the v ref input voltage when all digital inputs are high. feedthrough error error caused by capacitive coupling from v ref to output. feedthrough error limits are specified with all switches off. output capacitance capacitance from i out1 to ground. output leakage current current appearing at i out1 when all digital inputs are low, or at i out2 terminal when all inputs are high. general circuit information the DAC8143 is a 12-bit serial-input, buffered serial-output, multiplying cmos d/a converter. it has an r-2r resistor lad- der network, a 12-bit input shift register, 12-bit dac register, control logic circuitry, and a buffered digital output stage. the control logic forms an interface in which serial data is loaded, under microprocessor control, into the input shift regis- ter and then transferred, in parallel, to the dac register. in ad- dition, buffered serial output data is present at the sro pin when input data is loaded into the input register. this buffered data follows the digital input data (sri) by 12 clock cycles and is available for daisy-chaining additional dacs. an asynchronous clear function allows resetting the dac register to a zero code (0000 0000 0000) without altering data stored in the registers. a simplified circuit of the DAC8143 is shown in figure 1. an inversed r-2r ladder network consisting of silicon-chrome, thin-film resistors, and twelve pairs of nmos current-steering switches. these switches steer binarily weighted currents into
DAC8143 C8C rev. b esd protection the DAC8143 digital inputs have been designed with esd re- sistance incorporated through careful layout and the inclusion of input protection circuitry. figure 2 shows the input protection diodes. high voltage static charges applied to the digital inputs are shunted to the supply and ground rails through forward biased diodes. these protection diodes were designed to clamp the inputs well below dangerous levels during static discharge conditions. figure 2. digital input protection equivalent circuit analysis figures 3 and 4 show equivalent circuits for the DAC8143s in- ternal dac with all bits low and high, respectively. the ref- erence current is switched to i out2 when all data bits are low, and to i out1 when all bits are high. the i leakage current source is the combination of surface and junction leakages to the substrate. the 1/4096 current source represents the constant 1-bit current drain through the ladders terminating resistor. output capacitance is dependent upon the digital input code. this is because the capacitance of a mos transistor changes with applied gate voltage. this output capacitance varies be- tween the low and high values. dynamic performance analog output impedance the output resistance, as in the case of the output capacitance, varies with the digital input code. this resistance, looking back into the i out1 terminal, varies between 11 k w (the feedback re- sistor alone when all digital input are low) and 7.5 k w (the feedback resistor in parallel with approximately 30 k w of the r-2r ladder network resistance when any single bit logic is high). static accuracy and dynamic performance will be af- fected by these variations. figure 3. DAC8143 equivalent circuit (all inputs low) figure 4. DAC8143 equivalent circuit (all inputs high) the gain and phase stability of the output amplifier, board lay- out, and power supply decoupling will all affect the dynamic performance of the DAC8143. the use of a small compensation capacitor may be required when high-speed operational amplifi- ers are used. it may be connected across the amplifiers feedback resistor to provide the necessary phase compensation to criti- cally damp the output. the considerations when using high speed amplifiers are: 1. phase compensation (see figures 7 and 8). 2. power supply decoupling at the device socket and use of proper grounding techniques. output amplifier considerations when using high speed op amps, a small feedback capacitor (typically 5 pfC30 pf) should be used across the amplifiers to minimize overshoot and ringing. for low speed or static
DAC8143 C9C rev. b applications, ac specifications of the amplifier are not very criti- cal. in high speed applications, slew rate, settling time, open- loop gain, and gain/phase margin specifications of the amplifier should be selected for the desired performance. it has already been noted that an offset can be caused by including the usual bias current compensation resistor in the amplifiers noninvert- ing input terminal. this resistor should not be used. instead, the amplifier should have a bias current which is low over the tem- perature range of interest. static accuracy is affected by the variation in the dacs output resistance. this variation is best illustrated by using the circuit of figure 5 and the equation: v error = v os 1 + r fb r o ? ? ? ? figure 5. simplified circuit where r o is a function of the digital code, and: r o = 10 k w for more than four bits of logic 1, r o = 30 k w for any single bit of logic 1. therefore, the offset gain varies as follows: at code 0011 1111 1111, v error 1 = v os 1 + 10 k w 10 k w ? ? ? ? = 2 v os at code 0100 0000 0000, v error 2 = v os 1 + 10 k w 30 k w ? ? ? ? = 4/3 v os the error difference is 2/3 v os . since one lsb has a weight (for v ref = +10 v) of 2.4 mv for the DAC8143, it is clearly important that v os be minimized, us- ing either the amplifiers pulling pins, an external pulling net- work, or by selection of an amplifier with inherently low v os . amplifiers with sufficiently low v os include pmis op77, op97, op07, op27, and op42. interface logic operation the microprocessor interface of the DAC8143 has been design- ed with multiple strobe and load inputs to maximize inter- facing options. control signals decoding may be done on chip or with the use of external decoding circuitry (see figure 12). figure 6. timing diagram
DAC8143 C10C rev. b table i. DAC8143 truth table DAC8143 logic inputs input register/ digital output control inputs dac register control inputs stb 4 stb 3 stb 2 stb 1 clr ld 2 ld 1 DAC8143 operation notes 010 g xxx 01 g 0 x x x serial data bit loaded from sri 0 f 0 0 x x x into input register and digital output 2, 3 g 1 0 0 x x x (sro pin) after 12 clocked bits. 1xxx x 0 x x no operation (input register and sro) 3 xx1 x xxx1 reset dac register to zero code 0 x x (code: 0000 0000 0000) 1, 3 (asynchronous operation) 1 1 x no operation (dac register and sro) 3 1x1 1 0 0 load dac register with the contents of input register 3 notes 1 clr = 0 asynchronously resets dac register to 0000 0000 0000, but has no effect on input register. 2 serial data is loaded into input register msb first, on edges shown. g is positive edge, f is negative edge. 3 0 = logic low, 1 = logic high, x = dont care. serial data is clocked into the input register and buffered output stage with stb 1 , stb 2 , or stb 4 . the strobe inputs are active on the rising edge. stb 3 may be used with a falling edge clock data. serial data output (sro) follows the serial data input (sri) by 12 clocked bits. holding any strobe input at its selected state (i.e., stb 1 , stb 2 or stb 4 at logic high or stb 3 at logic low) will act to prevent any further data input. when a new data word has been entered into the input register, it is transferred to the dac register by asserting both load inputs. the clr input allows asynchronous resetting of the dac regis- ter to 0000 0000 0000. this reset does not affect data held in the input registers. while in unipolar mode, a clear will re- sult in the analog output going to 0 v. in bipolar mode, the out- put will go to Cv ref . interface input description stb 1 (pin 4), stb 2 (pin 8), stb 4 (pin 11)input register and buffered output strobe. inputs active on rising edge. selected to load serial data into input register and buff- ered output stage. see table i for details. stb 3 (pin 10)input register and buffered output strobe input. active on falling edge. selected to load serial data into input register and buffered output stage. see table i for details. ld 1 (pin 5), ld 2 (pin 9)load dac register inputs. ac- tive low. selected together to load contents of input register into dac register. clr (pin 13)clear input. active low. asynchronous. when low, 12-bit dac register is forced to a zero code (0000 0000 0000) regardless of other interface inputs.
DAC8143 C11C rev. b in many applications, the DAC8143s zero scale error and low gain error, permit the elimination of external trimming compo- nents without adverse effects on circuit performance. for applications requiring a tighter gain error than 0.024% at 25 c for the top grade part, or 0.048% for the lower grade part, the circuit in figure 8 may be used. gain error may be trimmed by adjusting r 1 . the dac register must first be loaded with all 1s. r1 is then adjusted until v out = Cv ref (4095/4096). in the case of an ad- justable v ref , r1 and r feedback may be omitted, with v ref ad- justed to yield the desired full-scale output. applications information unipolar operation (2-quadrant) the circuit shown in figures 7 and 8 may be used with an ac or dc reference voltage. the circuits output will range between 0 v and +10(4095/4096) v depending upon the digital input code. the relationship between the digital input and the analog output is shown in table ii. the v ref voltage range is the maxi- mum input voltage range of the op amp or 25 v, whichever is lowest. figure 7. unipolar operation with high accuracy op amp (2-quadrant) figure 8. unipolar operation with fast op amp and gain error trimming (2-quadrant) table ii. unipolar code table digital input nominal analog output (v out as shown msb lsb in figures 7 and 8) 1 1 1 1 1 1 1 1 1 1 1 1 C v ref 4095 4096 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 0 1 C v ref 2049 4096 ? ? ? 1 0 0 0 0 0 0 0 0 0 0 0 C v ref 2048 4096 ? ? ? = C v ref 2 0 1 1 1 1 1 1 1 1 1 1 1 C v ref 2047 4096 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 1 C v ref 1 4096 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 C v ref 0 4096 ? ? ? = 0 notes 1 nominal full scale for the circuits of figures 7 and 8 is given by fs = C v ref 4095 4096 ? ? ? ? . 2 nominal lsb magnitude for the circuits of figures 7 and 8 is given by lsb = v ref 1 4096 ? ? ? ? or v ref (2 C n )
DAC8143 C12C rev. b figure 9. bipolar operation (4-quadrant, offset binary) bipolar operation (4-quadrant) figure 9 details a suggested circuit for bipolar, or offset binary operation. table iii shows the digital input-to-analog output re- lationship. the circuit uses offset binary coding. twos comple- ment code can be converted to offset binary by software inversion of the msb or by the addition of an external inverter to the msb input. resistor r3, r4, and r5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient match. mismatching between r3 and r4 causes offset and full-scale error. calibration is performed by loading the dac register with 1000 0000 0000 and adjusting r1 until v out = 0 v. r1 and r2 may be omitted by adjusting the ratio of r3 to r4 to yield v out = 0 v. full scale can be adjusted by loading the dac register with 1111 1111 1111 and adjusting either the amplitude of v ref or the value of r5 until the desired v out is achieved. daisy-chaining DAC8143s many applications use multiple serial-input dacs that use nu- merous interconnecting lines for address decoding and data lines. in addition, they use some type of buffering to reduce loading on the bus. the DAC8143 is ideal for just such an ap- plication. it not only reduces the number of inter-connecting lines, but also reduces bus loading. the DAC8143 can be daisy- chained with only three lines: one data line, one clk line, and one load line, see figure 10. table iii. bipolar (offset binary) code table digital input nominal analog output msb lsb (v out as shown in figure 9) 1 1 1 1 1 1 1 1 1 1 1 1 + v ref 2047 2048 ? ? ? 1 0 0 0 0 0 0 0 0 0 0 1 + v ref 1 2048 ? ? ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 C v ref 1 2048 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 1 C v ref 2047 2048 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 C v ref 2048 2048 ? ? ? notes 1 nominal full scale for the circuits of figure 9 is given by fs = v ref 2047 2048 ? ? ? . 2 nominal lsb magnitude for the circuits of figure 9 is given by lsb = v ref 1 2048 ? ? ? .
DAC8143 C13C rev. b figure 10. multiple DAC8143s with 3-wire interface figure 11. analog/digital divider analog/digital division the transfer function for the DAC8143 connect in the multiply- ing mode as shown in figures 7 and 8 is: v o = C v in a 1 2 1 + a 2 2 2 + a 3 2 3 + ... a 12 2 12 ? ? ? ? where a x assumes a value of 1 for an on bit and 0 for an off bit. the transfer function is modified when the dac is connected in the feedback of an operational amplifier as shown in figure 11 and is: v o = v in a 1 2 1 + a 2 2 2 + a 3 2 3 + ... a 12 2 12 ? ? ? ? ? ? the above transfer function is the division of an analog voltage (v ref ) by a digital word. the amplifier goes to the rails with all bits off since division by zero is infinity. with all bits on the gain is 1 ( 1 lsb). the gain becomes 4096 with the lsb, bit 12, on. application tips in most applications, linearity depends upon the potential of i out1, i out2, and agnd (pins 1, 2 and 3) being exactly equal to each other. in most applications, the dac is connected to an external op amp with its noninverting input tied to ground (see figures 7 and 8). the amplifier selected should have a low input bias current and low drift over temperature. the amplifiers in- put offset voltage should be nulled to less than 200 m v (less than 10% of 1 lsb). the operational amplifiers noninverting input should have a minimum resistance connection to ground; the usual bias cur- rent compensation resistor should not be used. this resistor can cause a variable offset voltage appearing as a varying output er- ror. all grounded pins should tie to a single common ground point, avoiding ground loops. the v dd power supply should have a low noise level with no transients greater than +17 v. it is recommended that the digital inputs be taken to ground or v dd via a high value (1 m w ) resistor; this will prevent the accu- mulation of static charge if the pc card is disconnected from the system. peak supply current flows as the digital input pass through the transition region (see the supply current vs. logic input volt- age graph under the typical performance characteristics). the supply current decreases as the input voltage approaches the supply rails (v dd or dgnd), i.e., rapidly slewing logic signals that settle very near the supply rails will minimize supply current.
DAC8143 C14C rev. b DAC8143 interface to the 68000 figure 14 shows the DAC8143 configured to the 68000 micro- processor. serial data input is similar to that of the 6800 in fig- ure 12. figure 14. DAC8143 to 68000 m p interface DAC8143 interface to the 8085 the DAC8143s interface to the 8085 microprocessor is shown in figure 13. note that the microprocessors sod line is used to present data serially to the dac. data is strobed into the DAC8143 by executing memory write instructions. the strobe 2 input is generated by decoding an ad- dress location and wr . data is loaded into the dac register with a memory write instruction to another address location. serial data supplied to the DAC8143 must be present in the right-justified format in registers h and l of the microprocessor. figure 13. DAC81438085 interface interfacing to the mc6800 as shown in figure 12, the DAC8143 may be interfaced to the 6800 by successively executing memory write instruction while manipulating the data between writes, so that each write presents the next bit. in this example, the most significant bits are found in memory locations 0000 and 0001. the four msbs are found in the lower half of 0000, the eight lsbs in 0001. the data is taken from the db 7 line. the serial data loading is triggered by stb 4 which is asserted by a decoded memory write to a memory location, r/ w , and f 2. a write to another address location transfers data from input register to dac register. figure 12. DAC8143mc6800 interface
DAC8143 C15C rev. b outline dimensions dimensions are shown in inches and (mm). 16-lead plastic dip (n-16) 16 18 9 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead cerdip (q-16) 16 1 8 9 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.080 (2.03) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.840 (21.34) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 16-lead sol (r-16) 16 9 8 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0
000000000 printed in u.s.a. C16C

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